The present invention relates to the field of computers and particularly to computers that operate in accordance with the IBM ESA/390 architecture and particularly to timers in computers.
Timers are critical to computer system operation. The IBM ESA/390 architecture defines a number of timers and system implementations of that architecture may provide additional timers. The operation of such timers including the setting, resetting, stopping and starting becomes complex in large systems that have many different modes of operation and that operate with units of operation (UO).
The IBM ESA/390 architecture defines a unit of operation (UO) that is used to control the instants when an interruption can be examined and serviced. Interruptions can occur at any point in time; however, they are only examined and serviced during the interrupt processing time (IPT) between the end of one unit of operation and the start of the next unit of operation.
TABLE A depicts the relationship between units of operation and instruction processing time. ##STR1##
Most instructions consist of only one unit of operation. However, long and more complex or repetitive instructions such as MOVE LONG, COMPARE LOGICAL LONG, TEST BLOCK and UPDATE TREE consist of many units of operation.
The unit of operation is needed in large computer systems because of the need for having a reasonable response time for interruptions while avoiding complex instruction processing unit. If the interruptions have to be taken at any point in time during the instruction processing time, then the CPU design will be considerably more complex than if the interruptions are only taken at the end of instruction processing time.
ESA/390 architecture computers are controlled in part by a Program Status Word (PSW). The program-status word (PSW) includes the instruction address, condition code, and other information used to control instruction sequencing and to determine the state of the computer. The active or controlling PSW is called the current PSW. It governs the program currently being executed.
The CPU has an interruption capability, which permits the CPU to switch rapidly to another program in response to exception conditions and external stimuli. When an interruption occurs, the CPU places the current PSW in an assigned storage location, called the old-PSW location, for the particular class of interruption. The CPU fetches a new PSW from a second assigned storage location. This new PSW determines the next program to be executed. When it has finished processing the interruption, the interrupting program may reload the old PSW, making it again the current PSW, so that the interrupted program can continue.
The status of the CPU can be changed by loading a new PSW or part of a PSW. Control is switched during an interruption of the CPU by storing the current PSW, so as to preserve the status of the CPU, and then loading a new PSW.
A new or modified PSW becomes active (that is, the information introduced into the current PSW assumes control over the CPU) when the interruption or the execution of an instruction that changes the PSW is completed.
A storage key is associated with each 4K-byte block of storage that is available in the configuration. The storage key has the following format. ##STR2## The bit positions in the storage key are allocated as follows: